IEEE754 compliant 32-bit floating-point arithmetic unit
The high-speed computation execution unit demonstrates the best performance of FPGA IP!
We implemented a floating-point FIR calculation circuit on an FPGA and accelerated the algorithm from existing C source code. This unit has been adopted as an IP in customer-designed FPGAs. 【Features】 ● Equipped with a floating-point arithmetic unit compliant with IEEE 754 32-bit ● Has a specially customized pipeline structure that allows for high-speed execution of conventional C language expressions ● Optimized the structure to operate with small capacity and low-speed CLK while ensuring completion within the specified time
- 企業：エヌ・ディ・アール
- 価格：Other
